In Japanese patent laid-open No. 2003-100902 (Patent Reference 1), a semiconductor device with which a plurality of same channel type MOS's from which the impurity concentration in an extension layer and the impurity concentration in a pocket layer differ, and a breakdown voltage differs were formed on the same chip, and its manufacturing method are disclosed.
A semiconductor device with which a plurality of same channel type MOS's from which the impurity concentration in a channel region differs, and threshold value voltage differs were formed on the same chip, and its manufacturing method are disclosed in Japanese patent laid-open No. 2003-31682 (Patent Reference 2).
[Patent Reference 1] Japanese patent laid-open No. 2003-100902
[Patent Reference 2] Japanese patent laid-open No. 2003-31682